(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to fabricate a flash memory cell.
(2) Description of the Prior Art
The use of flash memory devices allow data to be stored in a non-volatile mode, and allows the stored data to be erased and rewritten as desired. The term flash refers to the ability to erase numerous memory cells simultaneously. However, if more aggressive processes and designs, resulting in smaller cell areas, are not implemented, performance and cost objectives, for flash memory chips, will be difficult to achieve.
This invention will teach a process for creating a self-aligned contact, (SAC), structure, for flash memory cells, resulting in a reduction in cell area. The use of the SAC structure, removes the need of providing contact holes to source regions, thus saving a photolithographic procedure. In addition the use of the symmetric SAC structure design, used in this invention, will be more conducive to future micro-miniaturization trends, than counterpart flash memory cells, fabricating using conventional contacts to source/drain regions. Prior art, such as Sung et al, in U.S. Pat. No. 5,734,607, describe a process for fabricating self-aligned bit line contact structures, whereas the present invention describes symmetric SAC structures, to both source, and to drain regions, which in turn have been self-aligned to stack gate structures, of a flash memory device, comprised with both control gate, and floating gate shapes.